Planar transistors are often used to fabricate integrated circuits. A planar MOS (metal oxide semiconductor) transistor has a diffused source electrode and drain electrode separated by a channel region. Overlying the channel region is a gate electrode that is separated from the channel region by a gate oxide. A planar bipolar transistor has a base electrode, a collector electrode, and an emitter electrode formed usually by diffusion technology. Planar transistors, although used and useful in many integrated circuit applications, are substrate area intensive and consume a large amount of substrate area per transistor. In addition, with integrated circuit geometries decreasing into sub-micron ranges, planar transistors have various disadvantages. At smaller geometries and thinner oxide thicknesses, well documented problems such as hot carrier injection, leakage currents, isolation, short channel behavior, diffusion junction depths, and channel length variations are major problems in planar transistors.
To overcome some of the disadvantages described above for planar transistors, elevated source and drain MOS transistors, lightly doped drain (LDD) MOS transistors, single polysilicon and double polysilicon planar bipolar transistors and other improvements were developed. Although the improvements reduced some of the disadvantages listed above, the improvements had some undesirable characteristics. The primary undesirable characteristic is the fact that the improved transistors were, in most cases, as area intensive or more area intensive than the planar transistor and in many cases are complex to manufacture.
Various approaches have been used to try to reduce transistor surface area and increase transistor packing density while at the same time reducing some of the adverse effects described above. The surrounding gate MOS transistor (SGT) was developed wherein a spacer gate and planar diffusions are used to form a vertical transistor. The SGT reduced some of the disadvantages that affect planar MOS transistors and reduced surface area due to a vertically positioned spacer gate. Topography problems and the geometry of the SGT usually result in source and drain contacts that are difficult to achieve and are difficult to consistently produce using sub-micron technology. In addition, doping of source regions, drain regions, and channel regions via implants can be difficult due to geometry and may require special processing.
In order to further increase circuit density, the thin film transistor (TFT) has been developed, especially for memory applications. Although small memory cell areas can result via the use of TFTs, TFTs are highly resistive and therefore not adequate for all applications.